Split gate non-volatile flash memory cells having a select gate, a floating gate, a control gate and an erase gate are well known in the art. See for example U.S. Pat. Nos. 6,747,310 and 7,868,375. An erase gate having an overhang over the floating gate is also well known in the art. See for example, U.S. Pat. No. 5,242,848. All three of these patents are incorporated herein by reference in their entirety for all purposes.
FIG. 1 shows a conventional pair of memory cells formed on a semiconductor substrate 10. Each memory cell includes a floating gate 14 disposed over and insulated from the substrate 10 by an insulation layer 12 (e.g., silicon dioxide (“oxide”)). A control gate 18 is disposed over and insulated from the floating gate 14 by an insulation layer 16 (e.g., ONO—oxide-nitride-oxide). Insulation layer 20 (e.g., silicon nitride (“nitride”)) is disposed over the control gate 10. Insulation layer 22 (e.g., oxide) is disposed over the insulation layer 20. Insulation layer 24 (e.g., nitride) is disposed over the insulation layer 22. A select gate (word line gate) 26 is disposed over and insulated from the substrate 10, and is laterally adjacent to the floating gate 14 and control gate 18. Spaced apart source and drain regions 28 and 30 respectively are formed in the substrate (having a conductivity type different than that of the substrate (or a well formed in the substrate)). An erase gate 32 is formed over and insulated from the source region 28 by an insulation layer 34 (e.g. oxide).
FIG. 2 shows a top plan view of the array of such memory cells. Each row of control gates 18 are formed or connected as a single line extending in the row direction (i.e. electrically connecting the entire row of control gates 18). Each row of select (word line) gates 26 are formed or connected as a single line extending in the row direction (i.e. electrically connecting the entire row of select gates 26). The columns of memory cells are insulated from each other by isolation regions 36 that extend in the column direction. For example, the well-known technique of forming trenches into the substrate surface, and filling the trenches will insulation material such as STI oxide, can be used to form the isolation regions 36. Each row of source regions (shared by two adjacent memory cells in the column direction) are formed as a continuous diffusion region that extends in the row direction through gaps G between adjacent isolation regions 36 in the column direction (i.e. electrically connecting an entire row of source regions 28). A conductive erase gate line 32 (shown in phantom in FIG. 2) extends over the source region diffusion 28 and is also shared by two adjacent memory cells in the column direction.
As device geometries continue to shrink, it becomes more difficult to control the gap G between the ends of the STI oxide facing each other (through which the source line diffusion extends). Additionally, with this configuration, there is excessive space taken up by the source line 28 and erase gate line 32 in order to ensure a workable critical dimension of gap G between the ends of adjacent STI isolation regions 36 (in the column direction), especially given the line-end rounding of the STI oxide.